U.S. Patent No. 6,954,848 - Prepared by Attorney David Tran for Intel Corporation and filed by Intel Corporation
Brief Description: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable. Methods and systems for identifying slowable instructions are described herein. Although the pipeline approach improves performance of the program by overlapping processing of the instructions, the instructions in the program are still processed in a logical sequence as dictated by the program. That is, each instruction is processed (e.g., fetch, decode, and execute) with an assumption that it is a critical or vital to the processing of the next one or more instructions. Each instruction is given highest available resources at a cost to complete its processing. However, this assumption may not necessary be correct for all instructions, and as such valuable resources may be wasted.