7152169 - Method for Providing Power Management on Multi-threaded Processors

Patent Counselors IP

U.S. Patent No. 7,152,169 - Prepared by Attorney David Tran for Intel Corporation and filed by Intel Corporation

Brief Description:  A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the physical processor is placed in a low power state.  Typically, mobile computer systems implement low power processor states to save power when the systems are idle. This may occur, for example, when the operating system (OS) has no threads in the running state or ready-to-run state. In situations where the computer systems include processors that do not support HT, a processor may be idle when there is no work to do. When the processor is idle, the OS may place the processor into the low power states (or C states). The way the OS policy is designed through ACPI is that the OS will cycle through the C states. For example, if the system is very busy and suddenly becomes idle, the OS will start placing the processor at the C1 state which is a very low rate C state that does not save very much power. When the processor is in the C1 state for a certain length of time, the OS will place the processor in the C2 state that may reduce more processor power. The OS then continues to progress through the C3 and C4 states when the processor has no work to do for a long time.

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