US Patent No. 6,892,284 - Prepared by Attorney David Tran for Intel Corporation and filed by Intel Corporation

Brief Description:  A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.  In accordance with one embodiment of the present invention, a memory in an interface is divided into multiple partitions. When memory space is required, a logical port may be assigned one or more partitions from a free pool of partitions. When a partition is not needed, it is returned to the free pool.   Each logical port is associated with a FIFO buffer. Each FIFO buffer may span multiple partitions assigned to that logical port. The multiple partitions may or may not be contiguous. The size of the FIFO buffer may be dynamic. For example, the size of a FIFO buffer may increase when more partitions are assigned to the logical port. Similarly, the size of the FIFO buffer may decrease when the logical port no longer needs the assigned partitions.